In recent years, much effort has been directed toward developing digital logic circuits which combine bipolar and CMOS technologies in a single integrated circuit. The combination of bipolar and CMOS technologies is particularly advantageous since the superior aspects of each may be exploited to yield optimal circuit performance.
For example, CMOS circuits have the advantages of extremely low quiescent power consumption, rail to rail output capability, high density, and a very high input impedance. Bipolar logic circuits, on the other hand, are useful in driving large capacitive loads, have fast switching capabilities, and feature better performance over temperature and power supply. These attributes have led to the development of a family of BiCMOS inverting logic circuits which employ bipolar transistors to drive output loads, while utilizing CMOS devices to perform the basic logic functions.
One problem with bipolar devices is that they suffer from a reliability problem when the voltage across the base and emitter junction (V.sub.BE) is negative. This reliability problem typically results in creation of base-emitter leakage current that is a function of negative base-emitter stress voltage and stress time. This leakage current degrades the circuit performance of the bipolar transistors. For example, consider the "bare-base" buffer circuit 10 of FIG. 1. If input node 11 is initially at high voltage level (e.g.+5 V), bipolar transistor 12 will be on, since the base is driven by the input signal and bipolar transistor 12 is connected as an emitter follower. Also, when input node 11 is at a high voltage level, a low voltage level will result at the gate of MOS transistor 15 due to inverter 16. Transistor 15 will thus be turned off, electrically isolating output node 14 from ground V.sub.SS. Output node 14 will then be at a high voltage level due to the emitter follower operation of bipolar transistor 12 with its collector coupled to the V.sub.DD mode. Conversely, when input node 11 switches to a low voltage level, transistor 12 is off, preventing any current flow from V.sub.DD mode 13 to output node 14. Transistor 15 is on, discharging the voltage at output node 14 to ground. However, input node 11 can go low faster than output node 14 due to the delay through inverter 16 and transistor 15. When this occurs, the base-emitter voltage V.sub.BE across bipolar transistor 12 will be negative (i.e. lower on the base side than the emitter side) causing the reliability voltage stress problem discussed above.
Similarly, a bipolar device cannot be used in a signal bus pre-charge circuit due to reliability problems caused by the negative V.sub.BE that can develop. For example, if the circuit 20 of FIG. 2 were used as a pre-charge circuit, transistor 22 would charge output node 24 so long as node 21 is at a high voltage state (logical one). This is due to the bipolar emitter follower between input node 21 and output node 24. Once the base is turned off (node 21 at a low voltage state, i.e. logical zero), a negative base-emitter voltage will result due to the remaining charge on output node 24.
What is needed is an integrated circuit combining CMOS and bipolar technologies which does not develop a negative V.sub.BE during operation. Such a circuit should be implemented with a minimum device count and should retain the advantages of both bipolar and CMOS technologies discussed above. Additionally, the circuitry used to protect the base should also be capable of tri-stating the bipolar device.